Job Description

Job Description: Integration Verification CW - Machine learning accelerators

***'s mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at *** are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities — we're just getting started.

*** AR/VR focuses on delivering ***'s vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. *** Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, firmware, and algorithms.

As an Integration Verification CW at *** AR/VR, you will work with a world-class group of researchers and engineers, and use your digital design, physical design, and verification skills to integrate state of the art machine learning accelerators into custom SOCs, and contribute to power and performance optimization through power aware simulations, gate level simulations and performance simulations. You will work closely with SOC and IP teams to execute functional and physical integration test plans.

This role is based in Sunnyvale, CA.

RESPONSIBILITIES

Execute verification plan for power and performance targets, and supporting tests for *** custom IP

Execute internal integration test plans, and support SOC vendor test plans and use case testing

Drive gate-level simulation health for internal netlists and SOC vendor netlists

Implement scalable power aware simulation and gate level simulation infrastructure leveraging test benches in System Verilog

Keep track of power state coverage metrics and bugs encountered and fixed

Implement self-testing directed and random tests

Support post silicon bringup and debug activities

Ability to communicate clearly

MINIMUM QUALIFICATIONS

2+ years of System Verilog OVM/UVM DV experience

2+ years of power aware verification

Gate-level simulation debugging experience

Knowledge with assertions (SVA) or others

Knowledge of digital ASICs design flows

Experience with at least 1 procedural programming language (C, C++, Python etc)

Bachelor's degree in Electrical Engineering or Computer Science or equivalent experience

PREFERRED QUALIFICATIONS

Experience as a digital design engineer

Experience with top-level integration

Masters in Electrical Engineering or Computer Science

Comments for Suppliers: Must be local to the area!!!

**MUST HAVE EXPERIENCE**

* SV/randomization, UVM( well be tested on TB Methodology knowledge)

* Python/Scripting

* CPU arch dv debug

* Regressions Triage/Debug. Comfortable navigating

* gate level sims preliminary

* Verdi/Waveform

Looking for individuals with mix of pre and post-Si/bringup experience

In need of candidates that have experience with integration verification including Power Aware simulation, UPF, and Gate level simulation that would be great

Focus areas should be pre-silicon verification (test planning, test writing, debug), System Verilog and UVM coding, Python scripting. Experience with low power simulation and Gate level simulations are a plus.