Job Description

If you are a Digital Design Engineer-FPGA-RTL-SOC with experience, please read on!

What You Will Be Doing

The Compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. This silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. We are growing our ASIC Design and Microarchitecture team within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using their digital design skills to implement and contribute to the development and optimization of power-efficient Computer Vision and ISP IPs.

Work with researchers and architects defining verification methodologies for each of the different core IP.

• Define and track detailed test plans for the different modules and top levels.
• Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
• Keep track of coverage metrics and bugs encountered and fixed.
• Implement self-testing directed and random tests.
• Support post silicon bringup and debug activities.
  

What You Need for this Position

• 3+ years of experience as a Digital Design Engineer and/or a Chip Lead.
• Experience in RTL coding, synthesis and/or SoC Integration.
• Experience in digital design {Architecture.
• Experience with at least 1 procedural programming language (C, C++, Python etc.).
• Bachelor's in Electrical Engineering/Computer Science or equivalent experience.
  

Preferred Qualifications

• Experience with computer vision or ISP accelerators.
• Experience with HLS flow for data path implementation.
• SystemVerilog OVM/UVM experience.
• Experience in SoC integration and ASIC architecture.
• Experience with low power design and optimization.
• Experience with design synthesis and timing optimization.
• Master's degree in Electrical Engineering/Computer Science.
  

What You Need for this Position

• Digital Design Engineer
• Digital Design
• RTL
• ASIC
• FPGA
• Synthesis
• SOC
• Integration
  

So, if you are a Digital Design Engineer-FPGA-RTL-SOC with experience, please apply today!

Email Your Resume In Word To

Looking forward to receiving your resume through our website and going over the position with you. Clicking apply is the best way to apply, but you may also:

Jonathan.Gilmor@Optello.com

• Please do NOT change the email subject line in any way. You must keep the JobID: linkedin : JG6-1646680 -- in the email subject line for your application to be considered.***
  

Jonathan Gilmor - Recruiting Manager - Optello

Applicants must be authorized to work in the U.S.

Optello is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.

Your Right to Work - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.

Optello will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.