Job Description

Meta Reality Labs Research is dedicated to the research and development required to bring virtual and augmented reality to billions of people around the world. We aspire to a vision of social AR and VR, where people are able to interact with each other across distances in a way that is indistinguishable from in-person interactions. Meta RLR is looking for a talented FPGA Engineer to accelerate the progression to authentic social presence in AR and VR. You will work in a dynamic cross-functional team including research scientists, research engineers, and software engineers, as well as hardware experts.

FPGA Engineer Responsibilities:

• Develop and improve FPGA system functionality and stability
• Develop and Customize FPGA/SOC board support package (BSP)
• Develop PC software tools for debugging and pipeline automation
• Design and prototype new system architecture for data collection and research
• Implement system design with internal engineers and vendors
• Engage in FPGA acceleration for image processing and computer vision algorithms
• Engage in prototype development with in house silicon

Minimum Qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or equivalent
• 5+ years of experience on designing FPGA/SoC based embedded systems
• 5+ years of experience in Verilog/SystemVerilog design and C/C++ firmware development
• 5+ years of experience with C++ and Python programming
• Proficiency in writing software for the UNIX/Linux platform
• Demonstrated skills in developing and testing high-speed video and audio streaming systems
• Experience on system automation and performance optimization
• Familiarity with low and high speed communication interfaces, such as I2C, UART, SPI, I2S, MIPI, USB, PCIe, AXI, general SerDes, CoaXPress, 100GE, and GigE Vision. Knowledge of CMOS camera, MEMS sensors, Schematic/PCB design, and signal integrity

Preferred Qualifications:

• 8+ years of experience on designing FPGA/SoC based embedded systems
• 3+ years of experience in image processing and computer vision algorithm optimization and FPGA implementation

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